A graphics board is a printed-circuit board that typically includes at least one graphics processor and other electronic components that process and display graphics or other video data in a computer system. FIG. 1 is a block diagram of a graphics board 100 that includes a graphics processor 105, as discussed in the aforementioned U.S. applications. Typically, one of the electronic components connected to the graphics processor 105 is a double-data-rate random-access memory (DDS RAM) chip 106. Both the graphics processor 105 and the DDR RAM 106 typically have high power requirements, as compared to other electronic components. For example, the graphics processor 105 typically requires 5–15 amps (A) of power at 1.6 volts (V), and the DDR RAM 106 typically 5–10 A and 10–20 A at 1.25 V and 2.5 V, respectively. Because the processor 105 and DDR RAM 106 have such high power requirements, pulse-width-modulated (PWM) switching power supplies 110a, 110b, and 110c are typically provided for the graphics processor 105 and the DDR RAM 106. A common power supply 108 feed the PWM switching power supplies 110a, 110b and 110c. Typically, the PWM power supplies 110a, 110b and 110c each includes a separate PWM-controller chip 112a, 112b and 112c, although these controllers can be integrated into the graphics processor 105 and DDR RAM 106 chips, respectively.
Ideally, the operating frequencies of the PWM power supplies 110a, 110b and 110c are the same. If, however, these frequencies are different, undesirable “beat” frequencies can result. A beat frequency is equal to the difference between the two frequencies. Unfortunately, the beat frequency can cause undesirable artifacts to appear in a video display.
A technique for reducing or eliminating the beat frequency is for two of the PWM controllers 112b and 112c (slaves) of the graphics board 105 to lock onto the PWM signal of the other PWM controller 112a (master) using a phase-lock loop (PLL). The slave PLLs can each generate one or more slave-PWM output signals that are phase locked to the master-PWM signal and that have the same frequency as the master-PWM signal.
As illustrated in FIG. 2, the master-PWM controller 112a provides output signals UG and LG to driver 120a, which provides a signal to integrator 122a. The output of the integrator 122a is V1. The master-PWM controller 112a also has signal LG connected as the input to a slave-PWM 112b. The output signals UG and LG of the slave-PWM 112b are provided to driver 120b, which provides a signal to integrator 122b. The output signal is V2. The slave-PWMs have a tendency to overcorrect if there are disturbances on the input signal. In other systems wherein the input signals to the PWM controllers are a crystal oscillator, there are no missed pulses. However, in PWM master/slave applications, there are missed pulses if the load current is stepped. If there are few missing pulses, it is possible that either the up or down pulses in the pulse width in the PLL will be very wide and drive the voltage control oscillator (VCO) to follow.
An example of this type of PLL is illustrated in FIG. 3 and disclosed in detail in the aforementioned U.S. applications. The input or reference signal IN2 at 202 is provided to a phase frequency detector (PFD) 200. The input signal 202 is compared against a feedback signal 204 coming from VCO 206. Depending upon the frequency difference, an up signal UP 208 or a down signal DN 210 is provided through a switching, gate or logic circuit 212 as UPG and DNG to a charge pump 220. The output of the charge pump 220 is provided through a filter 226 to the VCO 206. The output of VCO 206 is the output signal IN1 at 234, as well as feedback signal 204. A÷N counter 218 is responsive to the cycles of the PFD 220 to transmit the up/down signals on 208 and 210 through the gate circuit 212 to operate the charge pump 220. In the above-mentioned applications, the circuit 212 is shown as gated inverters, as well as multiplexes. In FIG. 3, they are illustrated by AND gates 214, 216. It should also be noted that the filter 226 has capacitor 228 in parallel with the series connection resistor 232 and capacitor 230. ÷N counter 218 is a decrementing counter and maintains a transmission signal having a width of a cycle of the PFD 220. It is the width of this signal through the circuit 212 which causes the overcorrection for the instability in the input signal at 202.